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Table 15–32 shows the Multiplier block inputs and outputs.
Table 15–32. Multiplier Block Inputs and Outputs
Chapter 15: Arithmetic Library
a
b
ena
aclr
r
Signal
Direction
Input
Input
Input
Input
Output
Description
Operand a.
Operand b.
Optional clock enable.
Optional asynchronous clear.
Result r.
Table 15–33 lists the parameters for the Multiplier block.
Table 15–33. Multiplier Block Parameters
Name
Bus Type
Input [number of bits].[]
Input [].[number of bits]
Number of Pipeline Stages
Both Inputs Have Same Bit
Width
Input b [number of bits].[]
Input b [].[number of bits]
Full Resolution for Output
Result
Output MSB
Output LSB
Output [number of bits].[]
Output [].[number of bits]
Use Dedicated Circuitry
DSP Builder Handbook
Value
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
AUTO, YES, NO
Description
The bus number format to use for the Multiplier block.
Specify the number of bits to the left of the binary point for input a (or
both input signals if set to have the same width).
Specify the number of bits to the right of the binary point for input a (or
both input signals if set to have the same width). This option applies only
to signed fractional formats.
The number of pipeline stages. The ena and aclr ports are available only
if the block is registered (that is, if the number of pipeline stages is greater
than or equal to 1).
Turn on if you want input a and input b to have the same bit width. When
off, additional fields are available to specify the number of bits to the left
and right of the binary point for input b .
Specify the number of bits to the left of the binary point for input b .
Specify the number of bits to the right of the binary point for input b . This
option applies only to signed fractional formats.
When on, the multiplier output bit width is full resolution. When off, you
can specify the number of bits for the output.
Specify the number of MSBs in the output for an integer bus.
Specify the number of LSBs in the output for an integer bus.
Specify the number of bits to the left of the binary point for the output r .
This option applies only to signed fractional formats.
Specify the number of bits to the left of the binary point for the output r .
This option applies only to signed fractional formats.
Use dedicated multiplier circuitry (if supported by your target device). A
value of AUTO means that the Quartus II software uses the dedicated
multiplier circuitry based on the width of the multiplier.
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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